Members and staff in Science and Technology often present their work at conferences
and universities around the world. We also welcome speakers from all over the
world to present their work at Almaden's weekly Science Colloquium
If you are a non-IBM employee and would like to attend the Science Colloquium, then...
Please contact Karen Deparini or Leann Sutton (ARCODS@us.ibm.com) by Thursday
afternoon to let us know to expect you on Friday morning. Please indicate your
professional affiliation and country of citizenship so that we can enter a "Visitor Access
Request" prior to your arrival. Also, if you would like to stay past the end of the seminar
(~11:45am) to talk with the speaker, please let us know.
Please plan to arrive at the Almaden lobby by 10:15am on Friday morning, and someone
will meet you in the lobby to escort you to the entrance of the Auditorium. Our Science
Colloquium seminars typically begin at 10:30am. You can find directions to our site
at http://www.almaden.ibm.com/almaden/visitorinfo.html.
Stephen Turner, Chief Technology Officer, Pacific Biosciences "Real Time DNA Sequencing From Single Polymerase Molecules"
SMRT (single molecule real time) DNA sequencing is a high-throughput method for eavesdropping on template-directed synthesis by DNA polymerase in real time. Pacific Biosciences has developed two critical technology components which enable this process: The first is phospholinked nucleotides where, in contrast to other sequencing approaches, the fluorescent label is attached to the terminal phosphate rather than the base. The enzyme cleaves away the fluorophore as part of the incorporation process, leaving behind completely natural double-stranded DNA. The second critical component is zero-mode waveguide (ZMW) confinement technology that allows single-molecule detection at concentrations of labeled nucleotides relevant to the enzyme. Through the combination of these innovations, our technology allows the speed, processivity, efficiency and fidelity of the enzyme to be exploited. We apply this technology to shotgun sequencing using a fast and simple sample preparation concept that facilitates whole-genome sequencing directly from genomic DNA.
Host: Greg Wallraff
Feb 12
Francesca Iacopi, Senior Scientist, IMEC, Belgium, iacopi@imec.be*
*presently guest Associate Professor at the University of Tokyo, Graduate School of Frontier Sciences, Japan, iacopi@plasma.k.u-tokyo.ac.jp "Nanowire-based microelectronics: some realistic perspectives for Si-compatible growth and applications"
The introduction of vertical nanostructures into microelectronics can bring the benefits of a larger flexibility in both device architecture and the combination of different semiconductor materials. For example, the electrical field in a vertical channel can be better controlled by an all-around gate [1]. Also, for sufficiently small diameters, the hetero-junction between two mismatched materials can theoretically sustain significantly higher misfit strains without generating dislocations in a nanowire as compared to the conventional planar configuration [2,3].
However, the bottom-up growth of semiconductor nanowires via an unconstrained vapor-liquid-solid (VLS) growth is generally not compatible with wafer-scale growth for silicon technologies because of the typical use of Au as a catalyst and the poor control of the wire orientation and the sharpness of hetero-junction.
Low melting point metals from the III and V groups are electrically compatible with Si and interesting catalyst candidates for VLS, but early attempts to use them for seeding growth of Si NW had failed. We demonstrate that Indium is an efficient VLS catalyst when chemical vapor deposition is employed in plasma -enhancement mode [4].
Additionally, we demonstrate a method to overcome the remaining shortcomings of VLS growth in a seedless templated fashion, combination of top-down and bottom-up techniques. We show the fabrication of segmented Ge/Si and Si1-xGex/Si nanowires with nm sharp interfaces based on selective epitaxial growth into a pre-defined template [5]. Implementing a suitable integration route, such process can directly be used on 300mm wafers for fabricating vertical gated hetero-junctions with an all around gate stack such as Tunnel-FETs [6], which show great promise for overcoming the limitations of conventional CMOS in very advanced technology nodes.
This work was partially supported by the EU programs NODE 015783 and SEA-NET Integrated Project IST-027982.
C.Thelander et al, Materials Today 9(10), pp.28-35, 2006.
J.Greer, Rev.Adv.Mater.Sci.13, 59-70, 2006
F.Glas, Phys Rev B 74, 505307, 2006
F.Iacopi et al, Nanotechnology 18(50), 505307, 2007
F.Iacopi et al., Mater. Res. Soc. Symp. Proc. Vol. 1178, 1178-AA04-04, 2009; F.Iacopi et al., invited at MRS-J, Yokohama, Japan, Dec.2009
A.S.Verhulst et al., J.Appl.Phys. 104, 064514, 2008
Host: Geraud Dubois
Feb 19
Winfried Wilcke, IBM Research - Almaden "Physics of Flying"
Host:Greg Wallraff
Feb 26
Professor Antonio Castro Neto "New Developments in Graphene
"