In a perfect world, the creation of a new storage class memory could proceed with no regard as to how the nanoscale features would eventually be fabricated. However, it is more than likely that such an SCM will in fact need to be carefully designed together with the process by which it will be eventually be fabricated en masse. In particular, one of the critical steps can be expected to be the definition of features at extremely high pitch (10-30nm).

Thus we collaborate closely with our colleagues throughout S&T, as well as with external partners, in order to understand the inevitable intermeshing between the lithographic scheme used to fabricate the device, the array architecture used to access the device, and the memory device itself. This work can be divided into three "plans":

Plan A: Enhanced Optical Lithography

Double expose, double etch Pitch-splitting As part of this area, we have developed a unique interference immersion lithography tool, called NEMO - you can read more about its accomplishments here.

Plan B: Imprint Lithography Plan C: Self-Assembly