For all the attractive features of a Storage Class Memory, such a memory will never be manufactured if the cost is not competitive. With silicon processing, low cost implies high density. In particular, we need to be designing memories that will have an effective cell-size of (significantly) less than 4F² per bit, where F represents the lithographic half-pitch.

Two ways to do this include

• a 3-D SCM. Although built with a pitch accessible with conventional lithography, the effective cell-size can be reduced to 4F²/(# of layers).

• a 2-D sub-lithographic SCM - Here a micro-to-nano addressing scheme provides an interface between the lithographic features at half-pitch F, and the sub-lithographic memory "sub-array" at a smaller pitch of F_s. By being able to address individual sub-lithographic (nano-) lines from a lithographically-defined (micro-) contact pad, the effective cell-size can be reduced by the number of memory elements in the dense sub-array.

This concept is independent of details of the memory node, yet since it is transistor-based, it can drive the large (mA/µm) currents required by a technology such as phase change memory. With this technique, we exploit the fact that the alignment of a lithography tool can be significantly more accurate than the minimum available pitch. However, this scheme does require a viable method for manufacturing sub-lithographic arrays - one example of the strong ties between Nanoscale Devices and Nanoscale Fabrication.